Shift Register

Requirements:

• WARP
• Active HDL

 

 

Program for Shift Register:
library IEEE;
use IEEE.std_logic_1164.all;
entity shiftreg is
port (
load: in STD_LOGIC;
sp: in STD_LOGIC;
clk: in STD_LOGIC;
si: in STD_LOGIC;
pi: in STD_LOGIC_VECTOR (3 downto 0);
s0: out STD_LOGIC;
p0: out STD_LOGIC_VECTOR (3 downto 0)
);
end shiftreg;
architecture shiftreg of shiftreg is
signal storage:std_logic_vector(3 downto 0) :="XXXX";
begin
process(clk)
variable i:integer := 1;
begin
if(load = '1')then
case sp is
when '1' =>
storage <= pi;
when '0' =>
if i<5 then
storage(i-1) <= si;
i :=i+1;
else
i:=1;
end if;
when others => null;
end case;
else
case sp is
when '1' =>
p0<=storage;
when '0' =>
if i<5 then
s0 <= storage(i-1);
i:=i+1;
else
i:=1;
end if;
when others => null;
end case;
end if;
end process;
end shiftreg;